Energy Efficient Implementation for Arithmetic Application in CMOS Full Adders

The overall view of this paper is to attain high speed, low power full adder cells with alternative logic cells that lead to have reduced power delay product. Two high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0. 18m CMOS technology, and were tested using a comprehensive test bench that allowed to measure the current taken from the full adder inputs, besides the current provided from the power supply. Post-layout simulations show that the proposed full adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area. Adder module is the core of many arithmetic operations such as addition, subtraction, multiplication and division with an alternative internal logic structure based on the multiplexing of the Boolean function. To determine the lowest power supply voltage of full adders can tolerate by its correct functionality. Delay in full adder relates the amount of energy spent during the realization of the determined task. The design of the full adder circuit in Micro wind tool that allow measuring the Delay, Area, Power Consumption and Speed.